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LT1162IN [Linear Systems]

Half-/Full-Bridge N-Channel Power MOSFET Drivers; 半/全桥N沟道功率MOSFET驱动器
LT1162IN
型号： LT1162IN
厂家： Linear Systems    Linear Systems
描述：

Half-/Full-Bridge N-Channel Power MOSFET Drivers
半/全桥N沟道功率MOSFET驱动器

驱动器 接口集成电路 光电二极管
文件： 总16页 (文件大小：229K)
中文：  中文翻译
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LT1160/LT1162  
Half-/Full-Bridge  
N-Channel  
Power MOSFET Drivers  
U
FEATURES  
DESCRIPTIO  
The LT®1160/LT1162 are cost effective half-/full-bridge  
N-channel power MOSFET drivers. The floating driver can  
drivethetopsideN-channelpowerMOSFETsoperatingoff  
a high voltage (HV) rail of up to 60V.  
■
Floating Top Driver Switches Up to 60V  
■
Drives Gate of Top N-Channel MOSFET  
above Load HV Supply  
■
180ns Transition Times Driving 10,000pF  
■
Adaptive Nonoverlapping Gate Drives Prevent  
The internal logic prevents the inputs from turning on the  
power MOSFETs in a half-bridge at the same time. Its  
unique adaptive protection against shoot-through cur-  
rents eliminates all matching requirements for the two  
MOSFETs. This greatly eases the design of high efficiency  
motor control and switching regulator systems.  
Shoot-Through  
■
Top Drive Protection at High Duty Cycles  
■
TTL/CMOS Input Levels  
■
Undervoltage Lockout with Hysteresis  
■
Operates at Supply Voltages from 10V to 15V  
■
Separate Top and Bottom Drive Pins  
Duringlowsupplyorstart-upconditions,theundervoltage  
lockout actively pulls the driver outputs low to prevent the  
power MOSFETs from being partially turned on. The 0.5V  
hysteresis allows reliable operation even with slowly vary-  
ing supplies.  
U
APPLICATIO S  
■
PWM of High Current Inductive Loads  
■
Half-Bridge and Full-Bridge Motor Control  
■
Synchronous Step-Down Switching Regulators  
TheLT1162isadualversionoftheLT1160andisavailable  
in a 24-pin PDIP or in a 24-pin SO Wide package.  
■
3-Phase Brushless Motor Drive  
■
High Current Transducer Drivers  
■
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.  
All other trademarks are the property of their respective owners.  
Class D Power Amplifiers  
U
TYPICAL APPLICATIO  
1N4148  
HV = 60V MAX  
+
1000µF  
100V  
1
14  
13  
12  
11  
+
+
SV  
PV  
BOOST  
T GATE DR  
T GATE FB  
T SOURCE  
12V  
10  
10µF  
25V  
IRFZ44  
C
1µF  
BOOST  
4
UV OUT  
IN TOP  
LT1160  
B GATE DR  
2
3
9
8
IN TOP IN BOTTOM T GATE DR B GATE DR  
IRFZ44  
PWM  
0Hz TO 100kHz  
L
L
L
H
L
L
L
H
L
L
H
L
L
IN BOTTOM B GATE FB  
SGND  
5
PGND  
6
H
H
H
1160 TA01  
11602fb  
1
LT1160/LT1162  
W W U W  
ABSOLUTE MAXIMUM RATINGS (Note 1)  
Supply Voltage (Note 2) ......................................... 20V  
Boost Voltage ......................................................... 75V  
Peak Output Currents (< 10µs) .............................. 1.5A  
Input Pin Voltages .......................... –0.3V to V+ + 0.3V  
Top Source Voltage ..................................... –5V to 60V  
Boost to Source Voltage ........................... –0.3V to 20V  
Operating Temperature Range  
Commercial .......................................... 0°C to 70°C  
Industrial ......................................... –40°C to 85°C  
Junction Temperature (Note 3)............................ 125°C  
Storage Temperature Range ................ –65°C to 150°C  
Lead Temperature (Soldering, 10 sec)................. 300°C  
U
W U  
PACKAGE/ORDER INFORMATION  
TOP VIEW  
ORDER PART  
ORDER PART  
TOP VIEW  
+
NUMBER  
NUMBER  
SV  
A
BOOST A  
1
2
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
+
SV  
IN TOP  
IN BOTTOM  
UV OUT  
SGND  
1
2
3
4
5
6
7
IN TOP A  
IN BOTTOM A  
UV OUT A  
T GATE DR A  
T GATE FB A  
BOOST  
14  
13  
3
T GATE DR  
LT1160CN  
LT1160CS  
LT1160IN  
LT1160IS  
LT1162CSW  
LT1162ISW  
T SOURCE A  
+
4
12 T GATE FB  
GND A  
PV A  
5
11 T SOURCE  
+
B GATE FB A  
+
B GATE DR A  
BOOST B  
6
PV  
10  
9
SV  
B
7
B GATE DR  
B GATE FB  
PGND  
IN TOP B  
IN BOTTOM B  
UV OUT B  
T GATE DR B  
T GATE FB B  
8
9
8
NC  
OBSOLETE  
PART NUMBERS  
T SOURCE B  
+
10  
11  
12  
N PACKAGE  
14-LEAD PDIP  
GND B  
PV B  
B GATE FB B  
B GATE DR B  
S PACKAGE  
LT1162CN  
LT1162IN  
14-LEAD PLASTIC SO  
N PACKAGE  
SW PACKAGE  
24-LEAD PDIP  
24-LEAD PLASTIC SO WIDE  
TJMAX = 125°C, θJA = 70°C/ W (N)  
TJMAX = 125°C, θJA = 110°C/ W (S)  
TJMAX = 125°C, θJA = 58°C/ W (N)  
TJMAX = 125°C, θJA = 80°C/ W (SW)  
Consult LTC Marketing for parts specified with wider operating temperature ranges.  
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. Test Circuit, TA = 25°C, V+ = VBOOST = 12V, VTSOURCE = 0V, CGATE  
3000pF. Gate Feedback pins connected to Gate Drive pins, unless otherwise specified.  
=
SYMBOL PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
+
I
DC Supply Current (Note 4)  
V
V
V
= 15V, V  
= 15V, V  
= 15V, V  
= 0.8V, V = 2V  
INBOTTOM  
7
7
7
11  
10  
11  
15  
15  
15  
mA  
mA  
mA  
S
INTOP  
INTOP  
INTOP  
+
+
= 2V, V  
= 0.8V  
= 0.8V  
INBOTTOM  
= 0.8V, V  
INBOTTOM  
+
I
Boost Current (Note 4)  
V
V
= 15V, V  
= 60V, V  
= 0.8V  
= 75V,  
3
4.5  
6
mA  
BOOST  
TSOURCE  
BOOST  
= V  
INTOP  
INBOTTOM  
V
V
Input Logic Low  
Input Logic High  
●
●
●
1.4  
1.7  
7
0.8  
V
V
IL  
2
IH  
I
Input Current  
V
= V  
= 4V  
25  
9.7  
8.8  
9.8  
9.2  
µA  
V
IN  
INTOP  
INBOTTOM  
+
+
V
V
V
V
V
V
V
V
Undervoltage Start-Up Threshold  
Undervoltage Shutdown Threshold  
8.4  
7.8  
8.8  
8.2  
8.9  
8.3  
9.3  
8.7  
UVH  
UVL  
+
+
V
Undervoltage Start-Up Threshold  
Undervoltage Shutdown Threshold  
V
V
= 60V (V  
= 60V (V  
– V  
– V  
)
)
V
BUVH  
BUVL  
BOOST  
BOOST  
TSOURCE  
TSOURCE  
BOOST  
TSOURCE  
V
BOOST  
TSOURCE  
11602fb  
2
LT1160/LT1162  
ELECTRICAL CHARACTERISTICS  
The ● denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C.Test Circuit, TA = 25°C, V+ = VBOOST = 12V, VTSOURCE = 0V, CGATE  
3000pF. Gate Feedback pins connected to Gate Drive pins, unless otherwise specified.  
=
SYMBOL PARAMETER  
CONDITIONS  
MIN  
TYP  
0.1  
MAX  
5
UNITS  
+
I
Undervoltage Output Leakage  
Undervoltage Output Saturation  
Top Gate ON Voltage  
V
V
V
V
V
V
V
= 15V  
●
●
●
●
●
●
●
µA  
V
UVOUT  
+
V
V
= 7.5V, I  
= 2.5mA  
0.2  
0.4  
12  
UVOUT  
OH  
UVOUT  
= 2V, V  
= 0.8V  
11  
11  
11.3  
11.3  
0.4  
V
INTOP  
INTOP  
INTOP  
INTOP  
INTOP  
INBOTTOM  
Bottom Gate ON Voltage  
Top Gate OFF Voltage  
= 0.8V, V  
= 0.8V, V  
= 2V  
= 2V  
12  
V
INBOTTOM  
V
0.7  
0.7  
200  
V
OL  
INBOTTOM  
Bottom Gate OFF Voltage  
Top Gate Rise Time  
= 2V, V  
= 0.8V  
0.4  
V
INBOTTOM  
t
t
t
t
t
t
(+) Transition, V  
= 0.8V,  
= 0.8V,  
= 0.8V,  
= 0.8V,  
= 0.8V,  
= 0.8V,  
= 0.8V,  
= 0.8V,  
= 2V,  
130  
ns  
r
INBOTTOM  
Measured at V  
(Note 5)  
TGATE DR  
Bottom Gate Rise Time  
Top Gate Fall Time  
V
(+) Transition, V  
●
●
●
●
●
●
●
●
●
●
●
90  
200  
140  
140  
500  
400  
600  
400  
600  
500  
500  
400  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
INBOTTOM  
INTOP  
Measured at V  
(Note 5)  
BGATE DR  
V
(–) Transition, V  
60  
f
INTOP  
INBOTTOM  
Measured at V  
(Note 5)  
TGATE DR  
Bottom Gate Fall Time  
V
(–) Transition, V  
60  
INBOTTOM  
INTOP  
Measured at V  
(Note 5)  
BGATE DR  
Top Gate Turn-On Delay  
Bottom Gate Turn-On Delay  
Top Gate Turn-Off Delay  
Bottom Gate Turn-Off Delay  
Top Gate Lockout Delay  
Bottom Gate Lockout Delay  
Top Gate Release Delay  
Bottom Gate Release Delay  
V
(+) Transition, V  
250  
200  
300  
200  
300  
250  
250  
200  
D1  
D2  
D3  
D4  
INTOP  
INBOTTOM  
Measured at V  
(Note 5)  
TGATE DR  
V
(+) Transition, V  
INTOP  
INBOTTOM  
Measured at V  
(Note 5)  
BGATE DR  
V
(–) Transition, V  
INBOTTOM  
INTOP  
Measured at V  
(Note 5)  
TGATE DR  
V
(–) Transition, V  
INTOP  
INBOTTOM  
Measured at V  
(Note 5)  
BGATE DR  
V
(+) Transition, V  
INTOP  
INBOTTOM  
Measured at V  
(Note 5)  
TGATE DR  
V
(+) Transition, V  
= 2V,  
INTOP  
INBOTTOM  
Measured at V  
(Note 5)  
BGATE DR  
V
(–) Transition, V  
= 2V,  
INBOTTOM  
INTOP  
Measured at V  
(Note 5)  
TGATE DR  
V
(–) Transition, V  
= 2V,  
INTOP  
INBOTTOM  
Measured at V  
(Note 5)  
BGATE DR  
+
+
Note 1: Stresses beyond those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to any Absolute  
Maximum Rating condition for extended periods may affect device  
reliability and lifetime.  
Note 4: I is the sum of currents through SV , PV and Boost pins.  
S
I
is the current through the Boost pin. Dynamic supply current is  
BOOST  
higher due to the gate charge being delivered at the switching frequency.  
See Typical Performance Characteristics and Applications Information  
sections. The LT1160 = 1/2 LT1162.  
Note 2: For the LT1160, Pins 1, 10 should be connected together. For the  
LT1162, Pins 1, 7, 14, 20 should be connected together.  
Note 5: See Timing Diagram. Gate rise times are measured from 2V to 10V  
and fall times are measured from 10V to 2V. Delay times are measured  
from the input transition to when the gate voltage has risen to 2V or  
decreased to 10V.  
Note 3: T is calculated from the ambient temperature T and power  
J
A
dissipation P according to the following formulas:  
D
LT1160CN/LT1160IN: T = T + (P )(70°C/W)  
J
A
D
LT1160CS/LT1160IS: T = T + (P )(110°C/W)  
J
A
D
LT1162CN/LT1162IN: T = T + (P )(58°C/W)  
J
A
D
LT1162CS/LT1162IS: T = T + (P )(80°C/W)  
J
A
D
11602fb  
3
LT1160/LT1162  
TYPICAL PERFORMANCE CHARACTERISTICS (LT1160 or 1/2 LT1162)  
W
U
DC Supply Current  
vs Supply Voltage  
DC + Dynamic Supply Current  
vs Input Frequency  
DC Supply Current  
vs Temperature  
14  
13  
12  
11  
10  
9
60  
50  
40  
30  
20  
10  
0
14  
13  
12  
11  
10  
9
+
50% DUTY CYCLE  
V
= 12V  
C
= 3000pF  
GATE  
BOTH INPUTS  
HIGH OR LOW  
V
V
= LOW  
INTOP  
INBOTTOM  
= HIGH  
+
BOTH INPUTS  
HIGH OR LOW  
V
= 20V  
V
V
= HIGH  
INTOP  
INBOTTOM  
+
= LOW  
V
= 15V  
V
V
= LOW  
INTOP  
INBOTTOM  
8
8
V
= HIGH  
= LOW  
INTOP  
= HIGH  
+
V
V
= 10V  
INBOTTOM  
7
7
6
6
5
5
1
10  
100  
1000  
–50 –25  
0
25  
50  
75  
125  
8
10  
12  
14  
16  
18  
22  
100  
20  
INPUT FREQUENCY (kHz)  
TEMPERATURE (°C)  
SUPPLY VOLTAGE (V)  
1160/62 G03  
1160/62 G02  
1160/62 G01  
DC + Dynamic Supply Current  
vs Input Frequency  
Undervoltage Lockout (V+)  
Undervoltage Lockout (VBOOST)  
60  
50  
40  
30  
20  
10  
0
13  
12  
11  
10  
9
13  
12  
11  
10  
9
50% DUTY CYCLE  
+
V
= 60V  
TSOURCE  
V
= 12V  
START-UP THRESHOLD  
SHUTDOWN THRESHOLD  
START-UP THRESHOLD  
SHUTDOWN THRESHOLD  
C
= 10000pF  
GATE  
8
8
C
= 3000pF  
GATE  
7
7
6
6
C
= 1000pF  
GATE  
5
5
4
4
1
10  
100  
1000  
–50 –25  
0
25  
50  
75  
125  
–50 –25  
0
25  
50  
75  
125  
100  
100  
INPUT FREQUENCY (kHz)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
1160/62 G04  
1160/62 G05  
1160/62 G06  
Input Threshold Voltage  
vs Temperature  
Top or Bottom Input Pin Current  
vs Temperature  
Top or Bottom Input Pin Current  
vs Input Voltage  
14  
13  
12  
11  
10  
9
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
+
+
+
V
V
= 12V  
= 4V  
V
= 12V  
V
= 12V  
IN  
V
HIGH  
V
LOW  
8
7
6
5
4
–50  
0
25  
50  
75 100 125  
–25  
4
8
10 11  
5
6
7
9
12  
–50 –25  
0
25  
50  
75  
125  
100  
TEMPERATURE (°C)  
INPUT VOLTAGE (V)  
TEMPERATURE (°C)  
1160/62 G08  
1160/62 G09  
1160/62 G07  
11602fb  
4
LT1160/LT1162  
W
U
(LT1160 or 1/2 LT1162)  
TYPICAL PERFORMANCE CHARACTERISTICS  
Bottom Gate Rise Time  
vs Temperature  
Bottom Gate Fall Time  
vs Temperature  
Top Gate Rise Time  
vs Temperature  
230  
210  
190  
170  
150  
130  
110  
90  
210  
190  
170  
150  
130  
110  
90  
300  
280  
260  
240  
220  
200  
180  
160  
140  
120  
100  
80  
+
+
+
V
= 12V  
V
= 12V  
V
= 12V  
C
= 10000pF  
LOAD  
C
= 10000pF  
= 3000pF  
LOAD  
C
= 10000pF  
LOAD  
C
C
= 3000pF  
LOAD  
C
= 3000pF  
LOAD  
50  
C
LOAD  
0
70  
C
= 1000pF  
0
LOAD  
50  
= 1000pF  
70  
LOAD  
C
= 1000pF  
100  
LOAD  
75  
50  
30  
–50 –25  
25  
50  
125  
–50 –25  
25  
75  
125  
–50 –25  
0
25  
50  
75  
125  
100  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
1160/62 G10  
1160/62 G11  
1160/62 G12  
Turn-Off Delay Time  
vs Temperature  
Top Gate Fall Time  
vs Temperature  
Turn-On Delay Time  
vs Temperature  
180  
160  
140  
120  
100  
80  
400  
350  
300  
250  
200  
150  
100  
400  
350  
300  
250  
200  
150  
100  
+
+
+
V
= 12V  
V
C
= 12V  
= 3000pF  
V
C
= 12V  
= 3000pF  
LOAD  
LOAD  
C
= 10000pF  
LOAD  
TOP DRIVER  
TOP DRIVER  
BOTTOM DRIVER  
C
= 3000pF  
LOAD  
BOTTOM DRIVER  
60  
40  
C
= 1000pF  
75  
LOAD  
50  
20  
–25  
0
25  
125  
–50  
100  
–50 –25  
0
25  
50  
75  
125  
–50 –25  
0
25  
50  
75  
125  
100  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
11160/62 G13  
1160/62 G14  
1160/62 G15  
Lockout Delay Time  
vs Temperature  
Release Delay Time  
vs Temperature  
400  
350  
300  
250  
200  
150  
100  
400  
+
+
V
C
= 12V  
= 3000pF  
V
C
= 12V  
= 3000pF  
LOAD  
LOAD  
350  
300  
250  
200  
150  
100  
TOP DRIVER  
BOTTOM DRIVER  
TOP DRIVER  
BOTTOM DRIVER  
–50 –25  
0
25  
50  
75  
125  
100  
–50 –25  
0
25  
50  
75  
125  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
1160/62 G16  
1160/62 G17  
11602fb  
5
LT1160/LT1162  
U
U
U
PIN FUNCTIONS  
LT1160  
LT1162  
SV+(Pin1):MainSignalSupply.Mustbecloselydecoupled  
SV+ (Pins 1, 7): Main Signal Supply. Must be closely  
to the signal ground Pin 5.  
decoupled to ground Pins 5 and 11.  
INTOP(Pin2):TopDriverInput.Pin2isdisabledwhenPin  
3 is high. A 3k input resistor followed by a 5V internal  
clamp prevents saturation of the input transistors.  
IN TOP (Pins 2, 8): Top Driver Input. The Input Top is  
disabledwhentheInputBottomishigh. A3kinputresistor  
followed by a 5V internal clamp prevents saturation of the  
input transistors.  
IN BOTTOM (Pin 3): Bottom Driver Input. Pin 3 is disabled  
when Pin 2 is high. A 3k input resistor followed by a 5V  
internalclamppreventssaturationoftheinputtransistors.  
IN BOTTOM (Pins 3, 9): Bottom Driver Input. The Input  
Bottom is disabled when the Input Top is high. A 3k input  
resistor followed by a 5V internal clamp prevents satura-  
tion of the input transistors.  
UVOUT(Pin4):UndervoltageOutput. OpencollectorNPN  
output which turns on when V+ drops below the  
undervoltage threshold.  
UVOUT(Pins4,10):UndervoltageOutput.Opencollector  
NPN output which turns on when V+ drops below the  
undervoltage threshold.  
SGND (Pin 5): Small Signal Ground. Must be routed  
separately from other grounds to the system ground.  
GND (Pins 5, 11): Ground Connection.  
PGND (Pin 6): Bottom Driver Power Ground. Connects to  
source of bottom N-channel MOSFET.  
B GATE FB (Pins 6, 12): Bottom Gate Feedback. Must  
connect directly to the bottom power MOSFET gate. The  
top MOSFET turn-on is inhibited until Bottom Gate Feed-  
back pins have discharged to below 2.5V.  
B GATE FB (Pin 8): Bottom Gate Feedback. Must connect  
directly to the bottom power MOSFET gate. The top  
MOSFET turn-on is inhibited until Pin 8 has discharged to  
below 2.5V.  
B GATE DR (Pins 13, 19): Bottom Gate Drive. The high  
current drive point for the bottom MOSFET. When a gate  
resistor is used it is inserted between the Bottom Gate  
Drive pin and the gate of the MOSFET.  
PV+ (Pins 14, 20): Bottom Driver Supply. Must be con-  
nected to the same supply as Pins 1 and 7.  
B GATE DR (Pin 9): Bottom Gate Drive. The high current  
drive point for the bottom MOSFET. When a gate resistor  
is used it is inserted between Pin 9 and the gate of the  
MOSFET.  
PV+ (Pin10):BottomDriverSupply. Mustbeconnectedto  
the same supply as Pin 1.  
T SOURCE (Pins 15, 21): Top Driver Return. Connects to  
the top MOSFET source and the low side of the bootstrap  
capacitor.  
T SOURCE (Pin 11): Top Driver Return. Connects to the  
top MOSFET source and the low side of the bootstrap  
capacitor.  
T GATE FB (Pins 16, 22): Top Gate Feedback. Must  
connect directly to the top power MOSFET gate. The  
bottomMOSFETturn-onisinhibiteduntilVTGF–VTSOURCE  
has discharged to below 2.9V.  
T GATE FB (Pin 12): Top Gate Feedback. Must connect  
directly to the top power MOSFET gate. The bottom  
MOSFETturn-onisinhibiteduntilV12–V11hasdischarged  
to below 2.9V.  
TGATEDR(Pins17, 23):TopGateDrive. Thehighcurrent  
drive point for the top MOSFET. When a gate resistor is  
used it is inserted between the Top Gate Drive pin and the  
gate of the MOSFET.  
TGATEDR(Pin13):TopGateDrive.Thehighcurrentdrive  
point for the top MOSFET. When a gate resistor is used it  
is inserted between Pin 13 and the gate of the MOSFET.  
BOOST (Pins 18, 24): Top Driver Supply. Connects to the  
high side of the bootstrap capacitor.  
BOOST (Pin 14): Top Driver Supply. Connects to the high  
side of the bootstrap capacitor.  
11602fb  
6
LT1160/LT1162  
U
U W  
FUNCTIONAL DIAGRA  
(LT1160 or 1/2 LT1162)  
BOOST  
TOP  
UV LOCK  
+
BIAS  
SV  
T GATE DR  
T GATE FB  
–
+
3k  
IN TOP  
5V  
5V  
2.9V  
T SOURCE  
+
PV  
3k  
IN BOTTOM  
BOTTOM  
UV LOCK  
–
+
UV OUT  
SGND  
B GATE DR  
2.5V  
LT1160  
PGND  
GND  
1/2 LT1162  
B GATE FB  
1160/62 BD  
(LT1160 or 1/2 LT1162)  
TEST CIRCUIT  
BOOST  
+
SV  
+
V/I  
+
V/I  
T GATE DR  
1µF  
3k  
IN TOP  
1µF  
3000pF  
+
+
T GATE FB  
T SOURCE  
IN BOTTOM  
V
UV OUT  
+
+
PV  
V
(LT1160)  
SGND  
PGND  
B GATE DR  
B GATE FB  
50Ω  
3000pF  
50Ω  
V
1160/62 TC01  
11602fb  
7
LT1160/LT1162  
W U  
W
TI I G DIAGRA  
2V  
IN TOP  
0.8V  
2V  
IN BOTTOM  
0.8V  
t
t
t
D2  
r
D3  
12V  
10V  
TOP GATE  
DRIVER  
0V  
2V  
t
t
f
t
D4  
D1  
t
r
t
t
D3  
D2  
12V  
10V  
BOTTOM  
GATE  
DRIVER  
2V  
0V  
1160/62 TD  
t
t
t
D4  
D1  
f
U
OPERATIO (Refer to Functional Diagram)  
The LT1160 (or 1/2 LT1162) incorporates two indepen-  
dentdriverchannelswithseparateinputsandoutputs.The  
inputs are TTL/CMOS compatible; they can withstand  
input voltages as high as V+. The 1.4V input threshold is  
regulated and has 300mV of hysteresis. Both channels are  
noninverting drivers. The internal logic prevents both  
outputs from simultaneously turning on under any input  
conditions. When both inputs are high both outputs are  
actively held low.  
UV detect block disables the high side channel when  
VBOOST – VTSOURCE is below its own undervoltage trip  
point.  
The top and bottom gate drivers in the LT1160 each utilize  
two gate connections: 1) a gate drive pin, which provides  
theturnonandturnoffcurrentsthroughanoptionalseries  
gate resistor, and 2) a gate feedback pin which connects  
directly to the gate to monitor the gate-to-source voltage.  
Whenever there is an input transition to command the  
outputs to change states, the LT1160 follows a logical  
sequence to turn off one MOSFET and turn on the other.  
First, turn-off is initiated, then VGS is monitored until it has  
decreased below the turn-off threshold, and finally the  
other gate is turned on.  
The floating supply for the top driver is provided by a  
bootstrap capacitor between the Boost pin and the Top  
Source pin. This capacitor is recharged each time the  
negative plate goes low in PWM operation.  
The undervoltage detection circuit disables both channels  
when V+ is below the undervoltage trip point. A separate  
11602fb  
8
LT1160/LT1162  
U
W U U  
APPLICATIONS INFORMATION  
Power MOSFET Selection  
Paralleling MOSFETs  
Since the LT1160 (or 1/2 LT1162) inherently protects the  
top and bottom MOSFETs from simultaneous conduction,  
there are no size or matching constraints. Therefore selec-  
tion can be made based on the operating voltage and  
RDS(ON) requirements. The MOSFET BVDSS should be  
greater than the HV and should be increased to approxi-  
mately (2)(HV) in harsh environments with frequent fault  
conditions.FortheLT1160maximumoperatingHVsupply  
of 60V, the MOSFET BVDSS should be from 60V to 100V.  
WhentheabovecalculationsresultinalowerRDS(ON)than  
is economically feasible with a single MOSFET, two or  
more MOSFETs can be paralleled. The MOSFETs will  
inherently share the currents according to their RDS(ON)  
ratio as long as they are thermally connected (e.g., on a  
common heat sink). The LT1160 top and bottom drivers  
can each drive five power MOSFETs in parallel with only a  
small loss in switching speeds (see Typical Performance  
Characteristics). A low value resistor (10Ω to 47Ω) in  
series with each individual MOSFET gate may be required  
to “decouple” each MOSFET from its neighbors to prevent  
high frequency oscillations (consult manufacturer’s rec-  
ommendations). If gate decoupling resistors are used the  
corresponding gate feedback pin can be connected to any  
one of the gates as shown in Figure 1.  
The MOSFET RDS(ON) is specified at TJ = 25°C and is  
generally chosen based on the operating efficiency re-  
quired as long as the maximum MOSFET junction tem-  
perature is not exceeded. The dissipation while each  
MOSFET is on is given by:  
P = D(IDS)2(1+∂)RDS(ON)  
Driving multiple MOSFETs in parallel may restrict the  
operating frequency to prevent overdissipation in the  
LT1160 (see the following Gate Charge and Driver Dissi-  
pation).  
Where D is the duty cycle and ∂ is the increase in RDS(ON)  
attheanticipatedMOSFETjunctiontemperature.Fromthis  
equation the required RDS(ON) can be derived:  
P
2
GATE DR  
LT1160  
GATE FB  
RDS ON  
=
(
)
D IDS 1+ ∂  
(
) (  
)
R *  
G
R *  
G
For example, if the MOSFET loss is to be limited to 2W  
when operating at 5A and a 90% duty cycle, the required  
RDS(ON) would be 0.089Ω/(1 + ∂). (1 + ∂) is given for each  
MOSFET in the form of a normalized RDS(ON) vs tempera-  
ture curve, but ∂ = 0.007/°C can be used as an approxima-  
tion for low voltage MOSFETs. Thus, if TA = 85°C and the  
available heat sinking has a thermal resistance of 20°C/W,  
the MOSFET junction temperature will be 125°C and  
∂ = 0.007(125 – 25) = 0.7. This means that the required  
RDS(ON) of the MOSFET will be 0.089Ω/1.7 = 0.0523Ω,  
which can be satisfied by an IRFZ34 manufactured by  
International Rectifier.  
*OPTIONAL 10Ω  
1160 F01  
Figure 1. Paralleling MOSFETs  
Gate Charge and Driver Dissipation  
A useful indicator of the load presented to the driver by a  
power MOSFET is the total gate charge QG, which includes  
the additional charge required by the gate-to-drain swing.  
QGisusuallyspecifiedforVGS=10VandVDS=0.8VDS(MAX)  
.
When the supply current is measured in a switching  
application, it will be larger than given by the DC electrical  
characteristics because of the additional supply current  
associated with sourcing the MOSFET gate charge:  
Transition losses result from the power dissipated in each  
MOSFET during the time it is transitioning from off to on,  
or from on to off. These losses are proportional to (f)(HV)2  
and vary from insignificant to being a limiting factor on  
operating frequency in some high voltage applications.  
⎛
⎞
⎛
⎞
dQG  
dt  
dQG  
dt  
ISUPPLY = IDC  
+
+
⎜
⎟
⎜
⎟
⎝
⎠
⎝
⎠
TOP  
BOTTOM  
11602fb  
9
LT1160/LT1162  
U
W U U  
APPLICATIONS INFORMATION  
The actual increase in supply current is slightly higher due  
to LT1160 switching losses and the fact that the gates are  
being charged to more than 10V. Supply Current vs  
Input Frequency is given in the Typical Performance  
Characteristics.  
lator period that the switch is on (switch conducting) and  
off (diode conducting) are given by:  
⎛
⎞
VOUT  
HV  
Switch ON =  
Total Period  
(
)
⎜
⎟
⎝
⎠
⎛
⎞
HV – VOUT  
HV  
The LT1160 junction temperature can be estimated by  
using the equations given in Note 2 of the Electrical  
Characteristics. For example, the LT1160IS is limited to  
less than 31mA from a 12V supply:  
Switch OFF =  
Total Period  
(
)
⎜
⎟
⎝
⎠
Note that for HV > 2VOUT the switch is off longer than it is  
on, making the diode losses more significant than the  
switch. The worst case for the diode is during a short  
circuit, when VOUT approaches zero and the diode con-  
ducts the short-circuit current almost continuously.  
TJ = 85°C + (31mA)(12V)(110°C/W)  
= 126°C exceeds absolute maximum  
In order to prevent the maximum junction temperature  
from being exceeded, the LT1160 supply current must be  
verified while driving the full complement of the chosen  
MOSFET type at the maximum switching frequency.  
Figure 2 shows the LT1160 used to synchronously drive a  
pair of power MOSFETs in a step-down regulator applica-  
tion, where the top MOSFET is the switch and the bottom  
MOSFET replaces the Schottky diode. Since both conduc-  
tionpathshavelowlosses,thisapproachcanresultinvery  
high efficiency (90% to 95%) in most applications. For  
regulators under 10A, using low RDS(ON) N-channel  
MOSFETseliminatestheneedforheatsinks.RGS holdsthe  
top MOSFET off when HVis applied before the 12V supply.  
Ugly Transient Issues  
In PWM applications the drain current of the top MOSFET  
is a square wave at the input frequency and duty cycle. To  
prevent large voltage transients at the top drain, a low ESR  
electrolytic capacitor must be used and returned to the  
power ground. The capacitor is generally in the range of  
25µF to 5000µF and must be physically sized for the RMS  
current flowing in the drain to prevent heating and prema-  
ture failure. In addition, the LT1160 requires a separate  
10µF capacitor connected closely between Pins 1 and 5  
(the LT1162 requires two 10µF capacitors connected  
between Pins 1 and 5, and Pins 7 and 11).  
One fundamental difference in the operation of a step-  
downregulatorwithsynchronousswitchingisthatitnever  
becomes discontinuous at light loads. The inductor cur-  
rent doesn’t stop ramping down when it reaches zero but  
actually reverses polarity resulting in a constant ripple  
current independent of load. This does not cause a signifi-  
cant efficiency loss (as might be expected) since the  
negative inductor current is returned to HV when the  
switch turns back on. However, I2R losses will occur  
under these conditions due to the recirculating currents.  
The LT1160 top source is internally protected against  
transients below ground and above supply. However, the  
gate drive pins cannot be forced below ground. In most  
applications, negative transients coupled from the source  
to the gate of the top MOSFET do not cause any problems.  
The LT1160 performs the synchronous MOSFET drive in a  
step-down switching regulator. A reference and PWM are  
required to complete the regulator. Any voltage mode or  
current mode PWM controller may be used but the LT3526  
is particularly well-suited to high power, high efficiency  
applications such as the 10A circuit shown in Figure 4. In  
higher current regulators a small Schottky diode across the  
bottomMOSFEThelpstoreducereverse-recoveryswitching  
losses.  
Switching Regulator Applications  
The LT1160 (or 1/2 LT1162) is ideal as a synchronous  
switch driver to improve the efficiency of step-down  
(buck) switching regulators. Most step-down regulators  
use a high current Schottky diode to conduct the inductor  
current when the switch is off. The fractions of the oscil-  
11602fb  
10  
LT1160/LT1162  
U
W U U  
APPLICATIONS INFORMATION  
HV  
BOOST  
+
T GATE DR  
T GATE FB  
SV  
PV  
+
12V  
LT1160  
R
GS  
REF PWM  
R
SENSE  
T SOURCE  
B GATE DR  
B GATE FB  
V
OUT  
+
OUT A  
OUT A  
IN TOP  
IN BOTTOM  
1160 F02  
Figure 2. Adding Synchronous Switching to a Step-Down Switching Regulator  
Motor Drive Applications  
The motor speed in these examples can be controlled by  
switching the drivers with pulse width modulated square  
waves. This approach is particularly suitable for micro-  
computers/DSP control loops.  
In applications where rotation is always in the same  
direction, a single LT1160 controlling a half-bridge can be  
used to drive a DC motor. One end of the motor may be  
connected either to supply or to ground as seen on Figure  
3. A motor in this configuration is controlled by its inputs  
whichgivethreealternatives:run,freerunningstop(coast-  
ing) and fast stop (“plugging” braking, with the motor  
shorted by one of the MOSFETs).  
HV  
LT1160  
+
BOOST  
T GATE DR  
T GATE FB  
T SOURCE  
B GATE DR  
B GATE FB  
PGND  
SV  
PV  
+
12V  
To drive a DC motor in both directions the LT1162 can be  
used to drive an H-bridge output stage. In this configura-  
tion the motor can be made to run clockwise, counter-  
clockwise, stop rapidly (“plugging” braking) or free run  
(coast) to a stop. A very rapid stop may be achieved by  
reversing the current, though this requires more careful  
design to stop the motor dead. In practice a closed-loop  
control system with tachometric feedback is usually  
necessary.  
IN TOP  
IN BOTTOM  
1160 F03  
Figure 3. Driving a Supply Referenced Motor  
11602fb  
11  
LT1160/LT1162  
TYPICAL APPLICATIONS  
U
0.1µF  
1µF  
+
4.7k  
C1  
0.1µF  
12V  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
10  
4.7k  
360Ω  
60V MAX  
10µF  
+
+
1N4148  
2200µF EA  
LOW ESR  
LT1160  
0.33µF  
1N4148  
2k  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
+
SV  
IN TOP  
IN BOTTOM T GATE FB  
BOOST  
IRFZ44  
T GATE DR  
0.022µF  
0.1µF  
1µF  
1k  
LT3526  
330k  
L*  
70µH  
R **  
S
0.007Ω  
1N4148  
0.1µF  
510Ω  
5V  
5k  
2N2222  
UV OUT  
SGND  
PGND  
NC  
T SOURCE  
+
+
5400µF  
LOW ESR  
1k  
PV  
IRFZ44 IRFZ44  
MBR360  
SHUTDOWN  
B GATE DR  
B GATE FB  
8
27k  
2.2nF  
f = 25kHz  
* MAGNETICS CORE #55585-A2  
30 TURNS 14GA MAGNET WIRE  
** DALE TYPE LVR-3  
ULTRONIX RCS01  
1160/62 F04  
Figure 4. 90% Efficiency, 40V to 5V 10A Low Dropout Voltage Mode Switching Regulator  
12V  
2200µF EA  
1N4148  
LOW ESR  
60V  
MAX  
+
+
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
10µF  
LT1160  
10k  
2k  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
2.2µF  
1µF  
+
SV  
IN TOP  
IN BOTTOM T GATE FB  
BOOST  
1N4148  
IRFZ44  
T GATE DR  
0.1µF  
1k  
330k  
L*  
47µH  
R **  
S
LT1846  
18k  
0.1µF  
0.007Ω  
UV OUT  
SGND  
PGND  
NC  
T SOURCE  
5V  
+
5400µF  
LOW ESR  
+
PV  
6800pF  
500k  
IRFZ44 IRFZ44  
25k  
1N4148  
10k  
5k  
B GATE DR  
B GATE FB  
MBR360  
100pF  
8
1k  
2N2222  
4700pF  
18k  
f = 40kHz  
* HURRICANE LAB  
HL-KM147U  
** DALE TYPE LVR-3  
ULTRONIX RCS01  
1160/62 F05  
Figure 5. 90% Efficiency, 40V to 5V 10A Low Dropout Current Mode Switching Regulator  
11602fb  
12  
LT1160/LT1162  
U
TYPICAL APPLICATIONS  
100µF  
10k  
150k  
IN  
0.0033µF  
1k  
12V  
60V MAX  
10µF  
5V  
1N4148  
0.1µF  
0.1µF  
1000µF  
+
LT1162  
1k  
24  
1
2
3
4
1
2
3
4
8
7
6
5
1
8
7
+
SV  
A
BOOST A  
IRFZ44  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
2
3
T GATE DR A  
T GATE FB A  
IN TOP A  
IN BOTTOM A  
UV OUT A  
GND A  
LT1015  
TC4428  
0.1µF  
6
5
330k  
4
100k  
1k  
T SOURCE A  
+
L*  
158µH  
IRFZ44  
10µF  
1N4148  
5
PV  
A
1k  
8
7
6
5
1
2
3
4
6
B GATE DR A  
BOOST B  
B GATE FB A  
+
1000µF  
10µF  
7
SV  
B
LT1016  
IRFZ44  
330k  
8
1µF  
0.1µF  
IN TOP B  
T GATE DR B  
T GATE FB B  
0.1µF  
9
IN BOTTOM B  
UV OUT B  
GND B  
LOAD  
10k  
10  
11  
12  
L*  
158µH  
T SOURCE B  
+
1k  
PV  
B
0.0033µF  
IRFZ44  
10k  
10k  
10µF  
1
14  
13  
12  
11  
10  
9
B GATE FB B  
B GATE DR B  
150k  
47µF  
2
3
4
–12V  
47µF  
LT1058  
10k  
95k  
10k  
0.1µF  
95k  
5
6
7
* Kool Mµ® CORE #77548-A7  
35 TURNS 14GA MAGNET WIRE  
= 100kHz  
47µF  
10k  
200k  
47µF  
+
8
f
CARRIER  
10k  
200k  
1160/62 F06  
Figure 6. 200W Class D, 10Hz to 1kHz Amplifier  
Kool Mµ is a registered trademark of Magnetics, Inc.  
11602fb  
13  
LT1160/LT1162  
U
PACKAGE DESCRIPTION  
N Package  
14-Lead PDIP (Narrow .300 Inch)  
(Reference LTC DWG # 05-08-1510)  
.770*  
(19.558)  
MAX  
14  
13  
12  
11  
10  
9
8
7
.255 ± .015*  
(6.477 ± 0.381)  
1
2
3
5
6
4
.300 – .325  
(7.620 – 8.255)  
.045 – .065  
(1.143 – 1.651)  
.130 ± .005  
(3.302 ± 0.127)  
.020  
(0.508)  
MIN  
.065  
(1.651)  
TYP  
.008 – .015  
(0.203 – 0.381)  
+.035  
.325  
.005  
(0.125)  
MIN  
–.015  
.120  
(3.048)  
MIN  
.018 ± .003  
(0.457 ± 0.076)  
.100  
(2.54)  
BSC  
+0.889  
8.255  
(
)
–0.381  
NOTE:  
INCHES  
MILLIMETERS  
N14 1002  
1. DIMENSIONS ARE  
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.  
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)  
N Package  
24-Lead PDIP (Narrow .300 Inch)  
(Reference LTC DWG # 05-08-1510)  
1.265*  
(32.131)  
MAX  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
10  
14  
11  
13  
12  
.255 ± .015*  
(6.477 ± 0.381)  
3
4
5
6
7
8
9
1
2
.300 – .325  
(7.620 – 8.255)  
.045 – .065  
(1.143 – 1.651)  
.130 ± .005  
(3.302 ± 0.127)  
.020  
(0.508)  
MIN  
.065  
(1.651)  
TYP  
.008 – .015  
(0.203 – 0.381)  
+.035  
.120  
(3.048)  
MIN  
.018 ± .003  
(0.457 ± 0.076)  
.100  
(2.54)  
BSC  
.325  
–.015  
+0.889  
8.255  
(
)
–0.381  
NOTE:  
INCHES  
N24 1002  
1. DIMENSIONS ARE  
MILLIMETERS  
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.  
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)  
OBSOLETE PACKAGE  
11602fb  
14  
LT1160/LT1162  
U
PACKAGE DESCRIPTION  
S Package  
14-Lead Plastic Small Outline (Narrow .150 Inch)  
(Reference LTC DWG # 05-08-1610)  
.337 – .344  
.045 ±.005  
(8.560 – 8.738)  
.050 BSC  
N
NOTE 3  
13  
12  
11  
10  
8
14  
N
9
.245  
MIN  
.160 ±.005  
.150 – .157  
(3.810 – 3.988)  
NOTE 3  
.228 – .244  
(5.791 – 6.197)  
1
2
3
N/2  
N/2  
.030 ±.005  
TYP  
RECOMMENDED SOLDER PAD LAYOUT  
7
1
2
3
4
5
6
.010 – .020  
(0.254 – 0.508)  
× 45°  
.053 – .069  
(1.346 – 1.752)  
.004 – .010  
(0.101 – 0.254)  
.008 – .010  
(0.203 – 0.254)  
0° – 8° TYP  
.050  
(1.270)  
BSC  
.014 – .019  
(0.355 – 0.483)  
TYP  
.016 – .050  
(0.406 – 1.270)  
S14 0502  
NOTE:  
1. DIMENSIONS IN  
INCHES  
(MILLIMETERS)  
2. DRAWING NOT TO SCALE  
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.  
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)  
11602fb  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-  
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.  
15  
LT1160/LT1162  
PACKAGE DESCRIPTION  
U
SW Package  
24-Lead Plastic Small Outline (Wide .300 Inch)  
(Reference LTC DWG # 05-08-1620)  
.050 BSC .045 ±.005  
.030 ±.005  
TYP  
.598 – .614  
(15.190 – 15.600)  
NOTE 4  
N
24 23 22 21 20 19 18  
16 15 14 13  
17  
N
.325 ±.005  
.420  
MIN  
.394 – .419  
(10.007 – 10.643)  
NOTE 3  
1
2
3
N/2  
N/2  
RECOMMENDED SOLDER PAD LAYOUT  
.291 – .299  
(7.391 – 7.595)  
NOTE 4  
2
3
5
7
8
9
10  
1
4
6
11 12  
.037 – .045  
.093 – .104  
.010 – .029  
(0.940 – 1.143)  
× 45°  
(2.362 – 2.642)  
(0.254 – 0.737)  
.005  
(0.127)  
RAD MIN  
0° – 8° TYP  
.050  
(1.270)  
BSC  
.004 – .012  
.009 – .013  
(0.102 – 0.305)  
NOTE 3  
(0.229 – 0.330)  
.014 – .019  
.016 – .050  
(0.356 – 0.482)  
TYP  
(0.406 – 1.270)  
NOTE:  
1. DIMENSIONS IN  
INCHES  
(MILLIMETERS)  
S24 (WIDE) 0502  
2. DRAWING NOT TO SCALE  
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.  
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS  
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.  
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)  
RELATED PARTS  
PART NUMBER  
DESCRIPTION  
COMMENTS  
LT1158  
Half-Bridge N-Channel Power MOSFET Driver  
Single Input, Continuous Current Protection and Internal Charge  
Pump for DC Operation  
LT1336  
Half-Bridge N-Channel Power MOSFET Driver with  
Boost Regulator  
Onboard Boost Regulator to Supply the High Side Driver  
LT1910  
Protected High Side MOSFET Driver  
V = 8V to 48V, Protected from –15V to 60V Transients, Auto  
IN  
Restart, Fault Indication  
LTC1922-1  
LTC1923  
Synchronous Phase Modulated Full-Bridge Controller  
Full-Bridge Controller for Thermoelectric Coolers  
Output Power from 50W to Kilowatts, Adaptive Direct Sense Zero  
Voltage Switching Compensates for External Component Tolerances  
High Efficiency, Adjustable Slew Rate Reduces EMI  
5mm × 5mm QFN and 28-Pin SSOP  
11602fb  
LT 0807 REV B • PRINTED IN USA  
LinearTechnology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7417  
16  
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com  
© LINEAR TECHNOLOGY CORPORATION 1995  

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